AbstractPart I. Correction of Cell Defects in Integrated Memories: This paper introduces two schemes to correct bit errors caused by defective memory cells in high speed, random access memory systems. The schemes are addressed to word-organized memories produced by the integrated technologies. One of the two schemes calls for encoding of input information, and the other does not. The schemes are simple, economical for the technologies concerned, and exhibit a regularity, which makes it possible to fabricate the necessary additional hardware within the same technology.
Part II. Correction of Temporary and Catastrophic Errors: A few classes of codes, suitable for error correction in high-speed memory systems, are presented. The codes have relatively simple parallel decoding nets. The codes may be used both for the correction of temporary and catastrophic errors.
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