AbstractEffective use of a processor requires the delivery of instructions and data at a sufficiently high rate to prevent stalls. Consequently, memories must be both large and fast. Current technology trends show that within the next few years the processor/memory interface will become a serious bottleneck that severely limits system performance.
Though DRAM speed will hold the processor/memory data bandwidth below acceptable levels it is possible to significantly increase the processor/memory information bandwidth. This can be done by increasing the "quality" of the data passed between memory and processor. The concept of increased data "quality" is the basis for the Rutgers CAM2000 design.
The CAM2000 architecture is a tree connected state machine consisting of four tightly coupled components; tree, leaf, memory, and I/O. It combines features of Associative Processing(AP), Content Addressable Memory (CAM), and Dynamic Random Access Memory (DRAM) in a single chip package that is not only DRAM compatible but capable of applying "simple" massively parallel operations to memory.
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